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IMAGE SENSOR SOLUTIONS
Functional Description
0-14dB
1.0
OVERVIEW
0-15dB
R
0-14dB
1.1 Light Capture and Conversion
The KAC-9617 contains a CMOS active pixel array consisting of
488 rows by 648 columns. This active region is surrounded by 8
columns and 8 rows of optically shielded (black) pixels as shown
in Figure.
Video
AMP
Analog pixel values
G
0-14dB
B
MUX
12 Bit A/D
Digital pixel data
640 columns, 480 rows
mono-chrome active pixels
8 columns, 8 rows
black pixels
8 columns, 8 rows
black pixels
Figure 9: Analog Signals In, Digital Data Out.
The digital pixel data is further processed to:
? remove defects due to bad pixels,
? compensate black level, before being framed and presented
on the digital output port. (see Figure 10).
do[11:0]
pclk
hsync
vsync
Figure 10. Digital Pixel Processing.
Figure 7: CMOS APS region of the KAC-9617
At the beginning of a given integration time the on-board timing
and control circuit will reset every pixel in the array one row at a
time as shown in Figure 7
1.2 Program and Control Interfaces
The programming, control and status monitoring of the KAC-
9617 is achieved through a two wire I 2 C compatible serial bus.
In addition, a slave address pin is provided (see Figure 11).
Note that all pixels in the same row are simultaneously reset, but
not all pixels in the array
a b c d e f g h i
j
k l m n o p q r
0
1
2
Register Bank
I 2 C Compatible
Serial I/F
sda
sclk
sadr
3
4
5
6
7
Analog Data Out
8
9
10
11
12
13
14
15
CDS/Shift Register
Figure 11. Control Interface to the KAC-9617.
Additional control and status pins: snapshot and external event
synchronization are provided allowing the latency of the serial
control port to be bypassed during single frame capture. An
interrupt request pin is also available allowing complex snapshot
operations to be controlled via an external micro-processor (see
Figure 12).
Figure 8. Sensor Addressing Scheme
At the end of the integration time, the timing and control circuit
will address each row and simultaneously transfer the integrated
Timing
Generator
extsyn
snapshot
value of the pixel to a correlated double sampling circuit and
then to a shift register as shown in Figure 8.
Once the correlated double sampled data has been loaded into
the shift register, the timing and control circuit will shift them out
one pixel at a time starting with column “a”.
The pixel data is then fed into an analog video amplifier, where a
user programmed gain is applied .
After gain adjustment the analog value of each pixel is con-
verted to 12 bit digital data as shown in Figure 9.
Figure 12. Snapshot & External Event Trigger Signals
www.kodak.com/go/imagers 585-722-4385
11
Email:imagers@kodak.com
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相关PDF资料
KAC-9627
IC SENSOR IMAGE VGA 48CLCC
KB-A100SRW
LIGHT BAR 660NM RED 8.89X3.81MM
KB-B100SRW
LIGHT BAR 660NM RED 19.05X3.81MM
KB-C100SRW
LIGHT BAR 660NM RED 8.89X8.89MM
KB-D100SRW
LIGHT BAR 660NM RED 8.89X3.81MM
KB-E100SRW
LIGHT BAR 660NM RED 8.89X3.81MM
KB-F100SRW
LIGHT BAR 660NM RED 19.05X3.81MM
KB-G100SRW
LIGHT BAR 660NM RED 8.89X8.89MM
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